Tomi Junnila
Almanpolku 2
21500 Piikkiö
Finland
Tel. +358 (0)50 568 9864
Last updated December 13, 2022
Family
Marital Status: Married
Children: 2 children, born 2004 and 2010
Language Skills
English | Excellent |
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Finnish | Native |
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French | Poor |
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Swedish | Poor |
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Professional Skills
SoC design | - Several SoC integration projects, including subsystem integration responsibility.
- Trace & Debug architecture, ARM CoreSight
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SoC verification | - SoC co-verification software design (C, C++ and assembly mostly for ARM and TMS320C55x processor cores)
- SoC co-simulation wakeup responsibility
- IP-level test bench development for reuse in ASIC-level verification
- Production test vector creation and validation
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Software design | - Object-Oriented Design
- Web application design (ASP.NET MVC & Core, , PHP)
- Windows application design (WPF)
- Low level driver design
- Qt C++ framework
- Some plain Windows API experience
- Database administration
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Programming languages | Assembly | ARM: extensive, TMS320C55x: some, x86: some |
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bash | good |
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C | extensive |
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C++ | extensive |
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C# | extensive |
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Java | some |
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perl | some |
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PHP | several years |
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Python | some |
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Ruby | limited |
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SystemVerilog | extensive |
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tcsh | some |
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VHDL | extensive |
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XSLT | some |
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Software frameworks | Angular 1 | some |
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ASP.NET Core | good |
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ASP.NET MVC 1-4 | good |
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ASP.NET Web API | good |
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React | limited |
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Work History
2008–present | Owner, Other Alien Software- Developing accounting and on-board ship stability software in C# on the Windows platform
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2015–present | Senior R&D Engineer, Nordic Semiconductor- SoC verification
- Subsystem verification
- Subsystem design & integration
- IP design
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2013–2015 | Software Engineer, Information Management, Cadmatic oy- Full stack software engineering
- CADMATIC eShare digital twin platform
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2007–2012 | Staff Engineer, SoC verification, STMicroelectronics / ST-NXP Wireless / ST-Ericsson- SoC verification
- Verification platform architecture and design in ARM assembly language, C and C++
- Verification planning
- Software implementation
- SoC wake-up
- SoC architecture design
- Participated in Trace & Debug architecture design
- IP architecture design
- Trace & Debug IPs:
- MIPI System Trace Protocol v2
- Trace Memory Manager for USB
- MIPI SneakPeek Protocol
- Industry standardisation
- Company representative in the MIPI Debug Workgroup and USB Debug Framework
- Author of the MIPI System Trace Protocol v2, MIPI Debug Adaptor for USB, and MIPI Debug Adaptor for UniPro
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1998–2007 | Digital ASIC design specialist, Nokia Technology Platform- SoC verification:
- SoC co-simulation wakeup responsibility
- Mostly in C and ARM1176JZF-S and TMS320C55x assembly languages
- SoC subsystem integration
- Production test vector creation and validation
- IP design:
- 3GPP searcher module
- System trace interface (including standardisation work into MIPI STP)
- Module-level test bench development for reuse in SoC-level verification
- Industry standardisation:
- Participating in the MIPI Debug Workgroup (then Trace & Debug Workgroup)
- Author of the MIPI System Trace Protocol v1
- Patent
- "A method for time-stamping messages", awarded 2008, with Ossi Lindvall (in use in the MIPI System Trace Protocol)
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1997–1998 | Software Designer, Ship Consulting Ltd Oy- Developed on-board ship stability software used on approximately 30 vessels worldwide
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1996–1998 | Linux System Administrator, Nisamest oy- Maintained the company's public web server
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1992–1996 | Software Designer, TOP-Case ky- Developed accounting and personal finance software in C, C++, Delphi, and x86 assembly language
- Technical support for Proxim wireless local area networks)
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Education
1993–2001 | University of Turku, Master of Science in Electronics and Information Technology Minor subjects: Physics, Mathematics and Computer Science Master Thesis titled "Designing a Rake Receiver for the Common Pilot Channels in 3GPP" (2000), eximia cum laude approbatur. |
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1990–1993 | Tuurepori secondary school, Turku, Finland. Baccalaureate spring of 1993, laudatur. |
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Military Service
1994–1995: signal corps, current rank senior lieutenant (reserve).
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